Abstract In this thesis, we present a set of scheduling algorithms that are used in designing core-based system-on-chips. Related techniques such as hardware /software codesign, and High-level-synthesis are defined. However, we selected some algorithms at system level and core level to implement them. They combined in system design methodology. Therefore, we used them for design exploration process. The methodology able to explore designs by scheduling them partitioning systems, and pipelining.Finally results obtained are encouraging to use the selected algorithm in designing efficient core-based system-on-chip systems.
مفيدة رمضان علي بلال (2010)

هذا البحث يقدم نماذج العيب للبرمجة بلغة السي أثناء تنفيد البرامج، نماذج العيب تزود تحليل للعيب/ الفشل موضحاً كيف يمكن للعيب في البرمجة بلغة السي أن يسبب تغيير حالة البيانات في البرنامج لتصبح حاطئة، وكيف أن تلك البيانات الخاطئة يمكن أن تستمر إلى الحالة النهائية للبرنامج، وبذلك يظهر الفشل Failure. نماذج العيب أيضاً تتضمن دليل لأنواع العيوب التي يعتقد أنها تمثل العيوب التي من المحتمل أن تكون مقدمة في البرامج من قبل مبرمجين يكتبون برامج لغة السي. كل نوع من هذه العيوب يكون موصوفاً في شروط حسب العيب الذي يظهر في محتوى برنامج لغة السي الأصلي وكذلك كيف يمكن أن يسبب التأثير في حالة البرنامج. أنواع العيوب تكون محددة من التحليل الدقيق لقواعد اللغة syntaxes ومعانيها semantics للبرامج المكتوبة بلغة السي. نماذج العيب يمكن أن تساعد المختبرين والمبرمجين لتحديد الأماكن في البرنامج التي غالباً ما تظهر فيها العيوب، نماذج العيب يمكن أن تكون أساساً جيداً لتصنيف العيب وإختبار التغيير وتفتيش البرنامج وتقييم إستراتيجيات الإختبار للبرامج المكتوبة بلغة السي. أمثلة معطاة لتبين النماذج الملائمة لهذه الأغراض. Abstract This thesis presents a fault models for C programming (Turbo C, version 3.0) in run-time of programs. The fault models provide a fault/failure analysis of how a fault in C programming can cause a data state change in the program to become corrupted, and how that erroneous data can propagate to the final state of the program, thereby manifesting a failure. The fault models also include a catalog of fault types that are believed to represent faults likely to be introduced in programs by programmers writing C code. Each type of fault is described in terms of how it appears syntactically in source code as well as in how it can cause an infection of program state. The fault types are identified from a careful analysis of the syntaxes and the semantics of C programs. The fault models can help testers and programmers identify places in a program where faults are most likely to appear, and identify what kinds of faults to look out for when using certain feature in C language. The fault models is claimed to be a good foundation for fault seeding, mutation testing, program inspections, and evaluation of testing strategies for C programs. Examples are given that demonstrate the model’s suitability for these purposes.
وفاء حسين محمود المصباحي (2010)

Abstract In practice, most SoCs are multiprocessor systems-on-chips (MPSoCs) because it is too difficult to design a complex system-on-chip without making use of multiple CPUs. MPSoCs are the latest picture of very large scale integration (VLSI) technology. The architecture of the system is generally tailored to the application rather than being a general-purpose chip. This in turn enforces designers to move beyond logic design into advanced computer architecture and parallel processing. In such architectures, cores are integrated via a custom or commercial interconnection network with a controller, timing and a function interface to the external world. Current state-of-the-art SoCs already embeds typical sub-systems such as digital signal processors (DSP), RAM, ROM, MPEG cores.The main goal of this thesis is to design an efficient switch for Fat-tree interconnection networks. In addition a useful survey study for interconnection networks architectures, technologies and routing algorithms was provided. The survey included in some details commonly used switching methods and virtual channel arrangements. The proposed switch structure has been validated by a software model.A set of algorithms and procedures have been developed to facilitate the switch functionality. Those procedures include the control of transmission of the packets from switch input buffer to switch output buffer and transferring packets from switch output buffer to neighboring switch input buffer. While the input/output link controllers take care of buffer assignments to flits (packet) and deals with buffer organization. More over, the algorithms include (i) the routing algorithm which is the least common ancestor routing algorithm, (ii) arbitration algorithm that based on round-robin technique.Therefore in this thesis we have proved the correctness of the functionality of the proposed switch in software model that have been written in C++ language. The obtained simulation results of the switch functionality in fat-tree of 16 nodes definitely declare the correctness of the proposed arbitration scheme as well as showing the efficiency of the routing algorithm. Finally, we can say that the fat-tree interconnection network is very good candidate to implement future NoC connectivity for current and future multiprocessor systems-on-chips (MPSoCs) designs due to its modular, flexible and regular structured design. In turn, these features are suitable as well for VLSI realizations.
أسماء شعبان العصار (2010)